1. Field of the Invention
This invention relates generally to transistors and small electronic devices including computer readable memory devices which can be read both statically, as found in-static RAM sensing schemes, or dynamically, as in dynamic RAMs which use precharge followed by signal development, and, more specifically, to methods for reducing noise when reading their information content.
2. Background Information
In non-volatile semiconductor memories, such as an EEPROM or Flash memory, the amount of data stored per memory cell has been increased in order to increase storage densities. At the same time, the operating voltages of such devices have decreased to reduce power consumption. This results in a greater number states stored in a smaller range of voltage or current values. As the voltage or current separation between data states decreases, the effects of noise become more important in the reading of these cells. For example, variations in the threshold value that are acceptable in a binary storage EEPROM cell operating at 5 volts may no longer be acceptable in a device operating at 3 volts with four or more bits storable per cell. Some consequences of noise, and methods for dealing with it, in a non-volatile memory are described in U.S. Pat. No. 6,044,019, which is hereby incorporated by reference.
Traditionally, physically larger transistors have been used for sensitive analog application, whereas digital circuits using physically small digital transistors operating in a binary mode have not been sensitive to the existing low levels of noise. Even 4 level storage non-volatile memories (2 bits/cell) have had large enough sensing margins to be generally immune to this noise in the majority of instances. However, as the scale of memory devices has continued to shrink, non-macroscopic effects, such as single electron or quantum effects, have become increasingly important and have exacerbated the noise problem.
Various aspects of the operation of such small scale devices are discussed in the following references, which are all hereby incorporated by reference:                [1] “Random Telegraph Noise in Deep-Submicrometer MOSFETS” by K. K. Huang, et. al., IEEE Electron Device Letters, Vol. 11, No. 2, February 1990;        [2] “Effects of oxide traps, interface traps, and border traps on metal-oxide-semiconductor devices” by D. M. Fleetwood, et. al., J. Appl. Phys., Vol. 73, No. 10, 15 May 1993;        [3] “Quantum Effects on the Extraction of MOS Oxide Traps by 1/f Noise Measurements” by Andrea Pacelli, et. al., IEEE Transactions on Electron Devices, Vol. 46, No. 5, May 1999, p. 1029ff;        [4] “In Depth Exploration of Si—SiO2 Interface Traps in MOS Transistors Using the Charge Pumping Technique” by Daniel Bauza, et. al., IEEE Transactions on Electron Devices, Vol. 44, No. 12, December 1997, p. 2262ff;        [5] “Critical Discussion on Unified 1/f Noise Models for MOSFETs” by Ewout P. Vandamme, et. al., IEEE Transactions on Electron Devices, Vol. 47, No. 11, November 2000, p. 2146ff;        [6] “A Solution for Current-Voltage Characteristics of Multiple Coupled Mesoscopic Tunnel Junctions”, by N. Mokhlesi et al., Superlattices and Microstructures, vol. 21, no. 1, pp. 15-19 (1997);        [7] “Capacitive nature of atomic-sized structures”, by G. J. Iafrate et al., Physical Review B VOL. 52, Number 15, pp. 10 733, 15 Oct. 1995-I;        [8] “1/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation”, by I. Bloom, et al., Applied Physics Letters 58(15) 15 Apr. 1991;        [9] “The decrease of “random telegraph signal” noise in metal-oxide-semiconductor field effect transistors when cycled from inversion to accumulation”, by B. Dierickx, et al., Journal of Applied Physics, 71 (4), 15 Feb. 1992;        [10] “MOSFET 1/f Noise Measurement Under Switched Bias Conditions”, by A. P. van der Wel, et al., IEEE Electron Device Letters, Vol. 21, No. 1, January 2000;        [11] “Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing”, by Eric A. M. Klumperink, et al., IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000, although no specific practical noise reduction technique for use in memory systems has been presented in these papers.        
Although the consequences of noise can be decreased by techniques such as those in U.S. Pat. No. 6,044,019 incorporated by reference above, or treated, with error correction code (ECC) or other equivalent error management such as is described in U.S. Pat. No. 5,418,752 which is hereby incorporated herein by this reference, memories could benefit from methods to reduce noise arising in the mesoscopic region between the macro- and microscopic ranges.